The present invention relates to non-volatile memory systems and more particularly to non-volatile memory access protocols.
When a memory component is accessed for storage or retrieval, various information is exchanged between the accessing entity and the memory. The accessing entity informs the memory whether the access is for the purpose of storage or retrieval, and the location of the stored data to be accessed. In some memory systems, the amount of data to be stored or retrieved in a single operation is also specified. The memory component in turn returns stored data when the accessing operation is for retrieval. When the accessing operation is for storage, the memory component receives the data to be stored.
A memory access protocol specifies the physical paths and timing of this information exchange. In one well known type of memory access protocol, address information and data are presented simultaneously on independent buses. A complete access operation occurs in a single cycle. A disadvantage of this approach is that each memory component must have a large number of pins to allow for connection to the two independent buses.
An alternative approach is the so-called multiple cycle command access protocol. In this type of protocol, a single collection of pins are used for communicating address information and data. A particular memory component is kept in a selected state for multiple cycles of the common bus while address information and data are exchanged between the accessing entity and the memory component.
Previous memory access protocols have been primarily developed for volatile memory as would be used for intermediate storage of software and data in a computer system. Non-volatile memory systems are becoming prevalent as replacements for disk drives in computer systems. These systems typically include large numbers of high capacity non-volatile memory components.
The desired characteristics of solid state non-volatile memory systems render previous memory access protocols problematic. Consider a non-volatile memory system that includes 64 non-volatile memory components, each storing 4 Megabytes of data. If each accessible data word is to be 16 bits wide, the data bus will require 16 lines and the address bus will require 20 lines. Thus, each non-volatile memory component will require 36 pins for bus operation only. Such a large pin count increases the size of each component package and thus the size of the whole non-volatile memory system. Furthermore, the large number of bus lines complicates board design in that each line must be routed to each component.
The multiple cycle command access protocol reduces the number of pins since address and data bus lines are shared. However, the pin count reduction comes at the expense of speed since the same bus must be used repeatedly for a single memory access. Speed has been increased in non-volatile memory systems by use of synchronous variants of the basic multiple cycle command access protocol, wherein the accessing entity specifies address information once but then receives a stream of successive words from the non-volatile memory component in response. Interleaving techniques are also known wherein while a first memory component is preparing a response to a memory access, other memory components on a common bus may be accessed. Neither synchronous techniques nor interleaving have been applied to non-volatile memory systems.
U.S. Pat. No. 5,430,859 discloses a serial protocol wherein address and data information are distributed among non-volatile memory using a very small number of lines. This protocol provides for simple packaging, routing and board layout but is very slow. What is needed is a non-volatile memory access protocol that provides high speed and moderate pinout and routing requirements.